The present invention generally relates to a direct memory access controller, and more particularly to a direct memory access controller having a plurality of descriptor formats which define the number and type of transfer information (descriptors) necessary for a direct memory access transfer.
Recently, it is required to transfer a large amount of data such as image data with extremely high speed between a data processing system such as a personal computer and a workstation, and an external unit such as a disc unit. It is also required to transfer a large amount of data between memories provided in the system with extremely high speed. A conventional data transfer is carried out under the control of a central processing unit (hereafter simply referred to as CPU) provided in the data processing apparatus. Therefore, the bit rate of the conventional data transfer depends on the processing speed of the CPU. From this viewpoint, it is impossible to transfer data at a speed in excess of the processing speed of the CPU. Further, it takes long to transfer a large amount of data even when the data is low-speed data. From the above-mentioned viewpoints, a direct memory access transfer is used which enables it to be possible to transfer data between the data processing apparatus and the external unit without using the CPU. Hereafter, direct memory access is simply referred to as DMA. The DMA transfer is intended to effectively process a large amount of data and high-speed data.
Generally, in the DMA transfer, data is transferred in accordance with descriptors which are information necessary for the DMA transfer. A descriptor format defines both the number and type of descriptors necessary for the DMA transfer, such as a source address, a destination address, and the number of bytes of data to be transferred. However, in the conventional DMA transfer, a single descriptor format is defined. In other words, all the DMA transfer operations are controlled by the single descriptor format. A plurality of types of DMA transfer are proposed. Examples of those are a register direct mode, and a descriptor chain mode, which is further classified into a sequential descriptor chain mode and a link descriptor chain mode. It is noted that all the information defined in the descriptor format are not always necessary to carry out the DMA transfer. However, in the conventional DMA transfer, all the information are stored in the memory, because a single descriptor format is defined. As a result, it is necessary to store the descriptors with a large amount of memory capacity. In addition, the data transfer speed is not high.